Cross-layer design and analysis of a low power, high density…
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- DOI 10.1109/iscas.2017.8050923
- OpenAlex ID W2756568087
- Type Conference-paper
- Language EN
- Published 01 May 2017
- Volume 39
- Pages 1–4
- Source IEEE International Symposium on Circuits…
- FWCI 7.59
- Countries 2
- Institutions 3
- Added 06 Oct 2017
- Updated 07 Oct 2026
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Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems
Conference-paper 2017 EN
STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) has attracted considerable attention of late since it is the most promising logic compatible nonvolatile memory that is suitable for advanced logic nodes (N28 and beyond) in terms of endurance, speed and power. Embedded STT-MRAM has thus been proposed as a candidate for emerging low standby-power connectivity systems such IoT (Internet-…
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UN Sustainable Development Goals
2 SDGsAuthors & Affiliations
10 authors| # | Author | Institutions | ORCID |
|---|---|---|---|
| 1 | Manu Komalan | Universidad Complutense de Mad… (ES) IMEC (BE) +1 | — |
| 2 | Sushil Sakhare | IMEC (BE) | |
| 3 | Trong Huynh-Bao | IMEC (BE) | |
| 4 | Siddharth Rao | IMEC (BE) | |
| 5 | Woojin Kim | IMEC (BE) | |
| 6 | Christian Tenllado | Universidad Complutense de Mad… (ES) | |
| 7 | José Ignacio Gómez | IMEC (BE) | |
| 8 | Gouri Sankar Kar | IMEC (BE) | |
| 9 | Arnaud Furnemont | IMEC (BE) KU Leuven (BE) | — |
| 10 | Francky Catthoor | Universidad Complutense de Mad… (ES) |
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