Parallel Multilevel Cell STT-MRAMs for Optimized Area Energy…
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- DOI 10.1109/tmag.2018.2814019
- OpenAlex ID W2796129752
- Type Article
- Language EN
- Published 02 Apr 2018
- Volume 54 (6)
- Pages 1–9
- Source IEEE Transactions on Magnetics
- Publisher IEEE Magnetics Society
- FWCI 0.69
- Countries 1
- Institutions 1
- Added 13 Apr 2018
- Updated 16 Oct 2026
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Parallel Multilevel Cell STT-MRAMs for Optimized Area Energy and Read–Write Operations
Article 2018 EN
Spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for the next generation embedded memory applications. The advent of a perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) device has made the STT-MRAM viable for low-power high-density on-chip memory architectures. However, intense research efforts are still required to optimi…
14
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0.69
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2 authors| # | Author | Institutions | ORCID |
|---|---|---|---|
| 1 | Sanjay Prajapati | Indian Institute of Technology… (IN) | |
| 2 | Brajesh Kumar Kaushik | Indian Institute of Technology… (IN) |
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