A virtual memory architecture to enhance STT-RAM performance…
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- DOI 10.1109/ccece.2016.7726657
- OpenAlex ID W2546565930
- Type Conference-paper
- Language EN
- Published 01 May 2016
- Volume 4
- Pages 1–6
- Source Conference proceedings - Canadian Confer…
- Publisher Institute of Electrical and Electro…
- Countries 1
- Institutions 1
- Added 10 Oct 2025
- Updated 26 Oct 2026
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A virtual memory architecture to enhance STT-RAM performance as main memory
Conference-paper 2016 EN
STT-RAM technology is becoming a popular alternative to both SRAM and DRAM. Several studies have proposed to use hybrid or pure STT-RAM architectures as on-chip caches as well as main memory. The main bulk of research targets improving the power consumption of this new memory technology especially due to the power hungry writes. In this paper we present a method to improve the power consumption of…
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UN Sustainable Development Goals
2 SDGsAuthors & Affiliations
4 authors| # | Author | Institutions | ORCID |
|---|---|---|---|
| 1 | Mohammad A. Ewais | American University in Cairo (EG) | |
| 2 | Mohamed A. Omran | American University in Cairo (EG) | — |
| 3 | Andrew Raafat | American University in Cairo (EG) | |
| 4 | Yousra Alkabani | American University in Cairo (EG) |
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