An Algorithm Based on AVS Encoding on FPGA Multi-Core Pipeli…
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- DOI 10.1109/iccis.2013.400
- OpenAlex ID W2010597126
- Type Conference-paper
- Language EN
- Published 01 Jun 2013
- Pages 1521–1524
- Source International Conference on Computationa…
- FWCI 0.55
- Countries 1
- Institutions 1
- Added 10 Oct 2025
- Updated 08 Oct 2026
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An Algorithm Based on AVS Encoding on FPGA Multi-Core Pipeline
Conference-paper 2013 EN
In view of the problem that the AVS encoding architecture on multi-cores have a high level of the intricacy, according to the data dependency of the encoding modules, combining with the advantages of the multi-core system in FPGA, a parallel algorithm based on GOP is proposed. This article built a single-core system based on XILINX FPGA first, then transplanted the AVS reference code RM5.2 to this…
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3 authors| # | Author | Institutions | ORCID |
|---|---|---|---|
| 1 | Fang Ji | Beijing University of Technolo… (CN) | |
| 2 | Xingyuan Li | Beijing University of Technolo… (CN) | |
| 3 | Chang-long Yang | Beijing University of Technolo… (CN) | — |
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