KS
Kang-Deog Suh

Highly Cited

61
Works
1,668
Citations
20
H-Index
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Author Statistics
  • OpenAlex ID A5112786953
  • i10-Index 29
  • 2-Yr Mean Citedness 0.00
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Kang-Deog Suh

Also known as: K. S. Suh, K. Suh, Kang Deog Suh, Kang-Deog SUH, Kang-Deog Suh

61

Total Works

1,668

Citations

20

H-Index

29

i10-Index

Citation & Works Trend by Year
25 years active
Top Research Topics
Semiconductor materials and devices (48) Low-power high-performance VLSI design (35) Advanced Data Storage Technologies (34) Advancements in Semiconductor Devices and Circuit Design (14) Ferroelectric and Negative Capacitance Devices (10)
Recent Publications
15 shown
Year Publication Title Citations Action
2025 Wafer-level magnetic shielding for highly reliable STT-MRAM with enhanced magnetic immunity Technical digest - International Electron Devices Meeting/Technical digest 0
2024 World-Most Energy-Efficient 14nm Automotive eMRAM Technology for High-Endurance Applications Technical digest - International Electron Devices Meeting/Technical digest 6
2022 Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 0
2021 28nm CIS-Compatible Embedded STT-MRAM for Frame Buffer Memory Technical digest - International Electron Devices Meeting/Technical digest 13
2020 28-nm 0.08 mm 2 /Mb Embedded MRAM for Frame Buffer Memory Technical digest - International Electron Devices Meeting/Technical digest 18
2020 Reliability of Industrial grade Embedded-STT-MRAM IEEE International Reliability Physics Symposium proceedings 7
2018 Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic Technical digest - International Electron Devices Meeting/Technical digest 94
2016 Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic Technical digest - International Electron Devices Meeting/Technical digest 98
2011 Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption Japanese Journal of Applied Physics 8
2010 A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory Technical digest - International Electron Devices Meeting/Technical digest 22
2010 Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories IEEE Journal of Solid-State Circuits 6
2010 32nm 3-bit 32Gb NAND Flash Memory with DPT (double patterning technology) process for mass production Symposium on VLSI Technology 8
2010 Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory IEICE Transactions on Electronics 1
2010 New scaling limitation of the floating gate cell in NAND Flash Memory IEEE International Reliability Physics Symposium proceedings 39
2010 Optimal cell design for enhancing reliability characteristics for sub 30 nm NAND Flash memory IEEE International Reliability Physics Symposium proceedings 3

Data source: OpenAlex API